The disclosure relates generally to conditional memory spreading for heterogeneous memory sizes.
In a symmetric multiprocessing computer system with processors and input/output (I/O), cache and memory hierarchy is designed to provide low latency and high bandwidth. When it comes to volatile, dynamic random access memory (DRAM) (e.g. dual in-line memory modules (DIMMs)), there are several factors to consider when designing the cache and memory hierarchy: intrinsic memory latency and performance (e.g. unloaded latency), queuing, and background operations (e.g., refresh/scrubbing/periodics). Queuing can adversely affect memory bandwidth. To minimize queuing, memory spreading can be included in the cache and memory hierarchy design.
In general, the symmetric multiprocessing computer system utilizes internal memory resources by spreading equally data traffic to portions of the internal memory resources. While evenly spreading data traffic across memory controllers often works for uniform DIMM sizes, when mixed DIMM sizes are used, this contemporary equal spreading can cause an unbalanced use of the internal memory resources, as each portion of the internal memory receives the same amount of data traffic regardless of availability and/or capability. The unbalanced use of the internal memory resources often results in uneven and inconsistent workload behaviors of the internal memory resources, along with pathological queuing issues as internal memory resources fill up that degrade memory performance.